--
-- VHDL Architecture ARMa_lib.OR_GATE.behav
--
-- Created:
--          by - Administrator.UNKNOWN (ECE-5BF87F3CFF5)
--          at - 22:06:35 10/28/2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

LIBRARY ARMa_lib;
USE ARMa_lib.ARMa_types.all;

ENTITY OR_GATE IS
   PORT( 
      CarryOut : IN     std_logic;
      SrcA     : IN     std_logic;
      clk      : IN     std_logic;
      SrcB     : OUT    std_logic
   );

-- Declarations

END OR_GATE ;

--
ARCHITECTURE behav OF OR_GATE IS
BEGIN
  SrcB <= SrcA or CarryOut;
END ARCHITECTURE behav;